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The Design and Evaluation Methodology of Dependable VLSI for Tamper Resistance

Principal Investigator
Takeshi Fujino (Ritsumeikan University / Professor)

Research Theme:
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} The smart cards, which keep money and personal information in their LSIs, are widespread in the social system. The dependability and security assurance of these LSI are critical issues. The attacker reveal secret information by analyzing the side-channel information such as power consumption and electro-magnetic field. Furthermore, the attacker could clone security LSIs by analyzing physical information. The purpose of this research is the design and evaluation methodology of dependable VLSI against these tamper attacks.

Open Documents

2009 Program Review (October 2009) (PDF 4,536kB)
DVLSI Workshop 2009 (December 2009) (PDF 1,745kB)
2010 Program Review1 (June 2010) (PDF 485kB)
2010 Program Review2 (October 2010) Team Reader Sato AIST (PDF 1,104kB)
DVLSI Workshop 2011/3 (March 2011) (PDF 2,980kB)
DVLSI Workshop 2011/12 (December 2011) (PDF 3,352kB)
DVLSI Workshop 2012/6 (June 2012) (PDF 1,020kB) (English document)
DVLSI International Symposium 2012/12 (December 2012) (PDF 2,175kB) (English document)

Annual Reports

2009 Annual Report (PDF 1,293kB)
2010 Annual Report (PDF 954kB)
2011 Annual Report (PDF 1,728kB)

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